Superlattice (SLC) structures are formed by selective deposition of thin layers of different semiconductor materials one above the other in a stacked arrangement to create a plurality of heterojunctions in the vertical or stacking direction. Electrical conduction will take place through the superlattice structure when trapped carriers absorb sufficient energy to escape the energy wells created at the interlayer junctions. If a transparent radiation window is provided for admitting photons into the junctions, a photosensitive superlattice structure can be fabricated for detecting photons having energy levels or frequencies above that of the energy band difference at the superlattice layer junctions. The energy band difference of the superlattice depends on the semiconductor materials selected to form each of its plural heterojunctions. Wavelength sensitivity can be established by selecting the semiconductor materials of each layer according to known energy band characteristics to create a desired energy level difference at the interlayer junctions.
One advantage of superlattice (SLS) sensors is that they can be tuned to specific infrared (IR) wavelengths by engineering the band structure. The high degree of wavelength tuneability supports operation at wavelengths that are not well supported by other IR sensor technologies. The SLS has a stack of wavelength tuned strained layers acting as pn junctions, and with proper electronic biasing the SLS can switch the sensitivity between two wavelengths. In addition to the benefits outlined above, that are a function of band structure, engineering SLS sensors show promise in the reduction of Auger currents.
Read out integrated circuit (ROIC) designs are constrained by the SLS sensors. The SLS sensors constrain the design of a ROIC in the following areas:                Pixel pitch/size        Imager/ROIC dimensions        ROIC well capacity        Signal to Noise Ratio (SNR) and resolution        Integration time/frame rate        Bias voltage requirements        SLS to ROIC mechanical interface        Operating Temperature        
The wavelength of imaged light and the limitations of the optics govern the range of pixel size. IR imaging is usually done in the medium wavelength infrared (MWIR) 2-5 μm to 8-10 μm bands. Pixel size is limited by the Airy disc, which defines the smallest spot that can be focused by an optical system with a circular aperture. For MWIR at 2 μm wavelength with an f/4 optical system.PITCHmin=1.22×λ×(f/#)=1.22×2 um×4=9.75 μm
SLS imagers are operating in the 5 μm to 14.5 μm wavelength range, which would set a minimum pixel size at about 25 um. The standard for SLS pixel size at the present time is about 30 μm, with some work being done in the 15 μm range.
Typically the pixel pitch determines the pixel size. At this time SLS imager pixel pitches are on the order of 30 μm, and this provides adequate area to design ROIC electronics to fit within the sensor footprint.
Many present SLS sensors have a size of 256×256 or 256×320 pixels. It is expected that in the near term the size will increase to 512×512 pixels as the SLS fabrication process improves. Long term expectations are for 1024×1024 pixel imagers.
SLS imagers typically have frame rates in the 30-60 Hz range. The frame rate and imager size determines the readout rate. SDM ADCs over sample the signal so that the maximum clock frequency is a product of the readout rate and the over sampling rate (OSR). For example, a 60 Hz frame rate for a 256×320 imager which is sliced into 64 pixel wide sections, with an oversampling ratio (OSR) of 64 would have a maximum sample clock frequency of:(64 columns×256 rows)×(60 fps)×(64 samples per pixel)=63 MHz.
This is easily within the range of current complementary metal oxide semiconductor (CMOS) design technologies. As the technology scales up to 1024×1024 imagers with readouts of 100 frames per second, CMOS will still be able to provide a ROIC solution but will require migration to deep submicron processes that can support high data rates. For example, a 100 Hz frame rate for a 1024×1024 imager which is sliced into 64 pixel wide sections, with an OSR of 64 would have a maximum sample clock frequency of:(64 columns×1024 rows)×(100 fps)×(64 samples per pixel)=420 MHz.
SLS imagers have lower Auger currents, but the state of the art at the present in SLS has higher dark currents than mercury cadmium telluride (HgCdTe) (MCT) IR imagers.
The SLS sensor element is a reversed biased pn junction photodiode. The output is a current and there is no inherent storage or integration of that current on the SLS sensor. This requires that the ROIC provide a capacitor and electronics to integrate and measure the total current output in a readout period. An average current output for the SLS reverse biased diode is 11 nA at a temperature of 85 K. The noise is the combination of sensor noise sources:                Auger Currents        Dark Current        Shot Noise        Detector 1/f noise and system noise sources:        Quantization Noise        Capacitor thermal noise (kTC Noise) from the integrating capacitor        Preamplifier 1/f Noise        Electrical noise        
The system noise is under control of the ROIC. With a SDM ADC, the OSR can be increased to reduce quantization noise, and it is possible to get 12-14 bit resolution. Shot noise is inherent to the sensor and IR source, and 1/f noise is inherent to both the sensor and electronics. The ratio of the signal and the sum of the various noise sources determine the signal to noise ratio (SNR). In general, the SNR improves with longer integration times. The integration time is a function of the capacity for charge storage in a pixel. For example, in a ROTC scheme that Lincoln Labs uses, the charge is reset after reaching a threshold which is equivalent to unlimited storage. In a ROIC with a single non-reset storage capacitor 20-50 million electrons of stored charge is a good goal. The maximum number of electrons stored is a common figure of merit for ROICs.
As mentioned above, the SLS imager requires biasing of the active imaging pn junction in each pixel. The bias can be externally supplied or the ROIC can provide biasing. The bias is on the order of 250-500 mV. SLS imagers can have several layers of pn junctions that are optically tuned to different wavelengths. By biasing the pn junction of interest in the reverse direction, the diode output and wavelength can be selected to be integrated and converted to a digital output. The ROIC should be able to detect the bias if it is externally provided and configure to operate with that bias, or alternatively generate a selectable bias.
The mechanical interface between the SLS and the ROIC has to adjust to the different coefficients of thermal expansion of the two materials. This may require an interface layer called a thermal expansion pedestal and wafer thinning as is done with MCT imagers.
The operating temperature of IR imagers requires the kT/q electron energy to be much less than the bandgap between the top of the valence band and the bottom of the conduction band. This is necessary to reduce thermal noise generated by electrons. SLS imagers typically operate in the 70 K-80 K range to reduce thermal noise.